The core of semiconductor memory includes a memory array for storing information, and the memory array is composed of building blocks such as semiconductors, and magnetic or ferroelectric memory cells. In general, the aforementioned memory array is a two-dimensional array composed of many memory cells, and each memory unit can be addressed by a word line and a bit line which are perpendicular to one another. A conventional word line select column is provided for turning on a memory unit, and a bit line select column is used for accessing (reading or writing) a memory unit. If both word line and bit line are turned on, it means that a memory unit having with electrically connected word line and bit line is selected.
As the semiconductor manufacturing capacity enhances, the size of the memory unit becomes increasingly smaller, and the overall size of the memory array becomes increasingly smaller as well. However, if the area of the memory array is reduced, the percentage of an area used for controlling peripheral circuits to write or read data of the memory array with respect to the total area will be increased significantly. For example, a driving circuit is arranged at a peripheral area of the memory array for driving the word line, and the driving circuit is situated at a rear end of the word line for receiving voltage. Compared with the arrangement of memory arrays in a memory unit, the arrangement of transistors of a driving circuit is generally very loose. As the size of the memory array is reduced to a micro scale, the percentage of area occupied by the driving circuit with respect to the total area of the memory circuit in accordance to the prior art will be increased greatly.
With reference to FIG. 1 for a circuit block diagram of a local word line driver of a conventional NOR flash memory, each local word line driver 100 comprises a PMOS transistor QA, a first NMOS transistor QB and a second NMOS transistor QC, and the PMOS transistor QA is connected to the first NMOS transistor QB in series, and the second NMOS transistor QC is connected to the PMOS transistor QA in series. A gate of the PMOS transistor QA is coupled to a gate of the first NMOS transistor and coupled to a control terminal GN. A drain of the PMOS transistor QA is coupled to a drain control terminal D that applies a voltage, and a source of the PMOS transistor QA is coupled to a drain of the first NMOS transistor QB and a source of the second NMOS transistor QC, and coupled to a local word line WL of the memory array. A drain terminal of the first NMOS transistor QB is coupled to a source of the second NMOS transistor QC, and coupled to the local word line WL. A source of the first NMOS transistor QB is coupled to a source control terminal S. A gate of the second NMOS transistor QC is coupled to another control terminal GP. The aforementioned circuit is used for supplying read, program, erase biased voltage to a word line.
Therefore, three MOS transistors used for forming a local word line driver in accordance with the prior art occupy much area of the whole circuit. As the size of the memory cell arrays is reduced to the micro scale, it is unfavorable to have a word line driver occupying too much area.